Channel Characterization for Chip-scale Wireless Communications within Computing Packages

Wireless Network-on-Chip (WNoC) appears as a promising alternative to conventional interconnect fabrics for chip-scale communications. WNoC takes advantage of an overlaid network composed by a set of millimeter-wave antennas to reduce latency and increase throughput in the communication between cores. Similarly, wireless inter-chip communication has been also proposed to improve the information transfer between processors, memory, and accelerators in multi-chip settings. However, the wireless channel remains largely unknown in both scenarios, especially in the presence of realistic chip packages. This work addresses the issue by accurately modeling flip-chip packages and investigating the propagation both its interior and its surroundings. Through parametric studies, package configurations that minimize path loss are obtained and the trade-offs observed when applying such optimizations are discussed. Single-chip and multi-chip architectures are compared in terms of the path loss exponent, confirming that the amount of bulk silicon found in the pathway between transmitter and receiver is the main determinant of losses.Comment: To be presented 12th IEEE/ACM International Symposium on Networks-on-Chip (NOCS 2018); Torino, Italy; October 201

Industrial and technical aspects of chip embedding technology

Embedding of semiconductor chips into organic substrates allows a very high degree of miniaturization by stacking multiple layers of embedded components, superior electrical performance by short and geometrically well controlled interconnects as well as a homogeneous mechanical environment of the chips, resulting in good reliability. At PCB manufacturing level, 50 mum thin chips have been embedded with pitches up to 200 mum in up to 18ldquotimes24rdquo panels. Embedding of chips at 100 mum pitch has been achieved at prototype level. Further developments of chip embedding can extend to even finer pitches without redistribution methods only with concurrent developments in ultra fine line patterning, plating methods and chemistries, assembly machines. New manufacturing processes should combine PCB processing and die assembly in one production line in order to benefit the most from this combination without the difficulties of transport between different manufacturing plants. Furthermore, new testing methodologies will be developed and a new supply chain will be created due to incorporation of embedding technologies to PCB production. This paper discusses in detail the technology and manufacturing challenges arisen from the integration of embedding technologies to PCB manufacturing processes

Engineer the Channel and Adapt to it: Enabling Wireless Intra-Chip Communication

Ubiquitous multicore processors nowadays rely on an integrated packet-switched network for cores to exchange and share data. The performance of these intra-chip networks is a key determinant of the processor speed and, at high core counts, becomes an important bottleneck due to scalability issues. To address this, several works propose the use of mm-wave wireless interconnects for intra-chip communication and demonstrate that, thanks to their low-latency broadcast and system-level flexibility, this new paradigm could break the scalability barriers of current multicore architectures. However, these same works assume 10+ Gb/s speeds and efficiencies close to 1 pJ/bit without a proper understanding on the wireless intra-chip channel. This paper first demonstrates that such assumptions do not hold in the context of commercial chips by evaluating losses and dispersion in them. Then, we leverage the system's monolithic nature to engineer the channel, this is, to optimize its frequency response by carefully choosing the chip package dimensions. Finally, we exploit the static nature of the channel to adapt to it, pushing efficiency-speed limits with simple tweaks at the physical layer. Our methods reduce the path loss and delay spread of a simulated commercial chip by 47 dB and 7.3x, respectively, enabling intra-chip wireless communications over 10 Gb/s and only 3.1 dB away from the dispersion-free case.Comment: 12 pages, 10 figures. IEEE Transactions on Communications Journal, 202

Modular power electronics, realized by PCB embedding technology: Presentation held at Productronica 2017, 14.11. bis 17.11.2017, München

This paper will describe the use of embedded die technologies for various application fields. The main focus of the paper will be the development work within the European funded project EmPower, which concentrates on power electronic applications. Here, three different power levels are of interest: - 50W single die packages with fast rectifier diodes - 500W power modules for electric bicycle application - 50kW power modules for HEV and EV application All three application fields are based on a similar concept. The so called power core provides the base for the package/module. This power core contains the embedded semiconductor(s) and is manufactured using printed circuit board processing on a large panel format of 18 by 24 inches. Electrical contacts to the embedded dies are made by laser drilled micro vias and copper filling. A major advantage of such a direct copper contact, compared to the conventionally used wire bond, is its high reliability and the improved electrical performance. By the reduction of the inductance of these interconnects, switching losses can be reduced significantly, allowing an improved and faster switching. For the higher power modules additionally thermal management is required. Here a construction of IMS substrates and the power core is chosen. This construction enables a double sided cooling and also the electrical isolation of the module to the cooler. The connection between power core and IMS substrates is made by low temperature and low pressure Ag sintering. All three applications fields will be described in detail. This will cover the development of the manufacturing process for all three power class demonstrators, as well as detailed structural analysis and reliability testing. The development work toward highly reliable modules will be discussed in depth. Finally the resulting demonstrators for 50W, 500W and 50kW power application and their characteristics will be presented in detail

Next generation system in a package manufacturing

The continuous miniaturization of silicon dies and the need for a further package size reduction, with an equal or better performance and reduced manufacturing cost, are the main drivers for new packaging concepts. The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and by that, the third dimension will be available for further layers or assemblies. This paper will illustrate the necessary process steps of the embedded chip technology, which is based on printed circuit board manufacturing processes, and will also demonstrate the transfer of the technology from a smaller size lab scale equipment environment to an industrial comparable process line, capable of processing large panel formats up to 18? x 24?. Furthermore results of technology developments toward ultra-fine line and ultra-fine pitch will be presented

Technical challenges of stencil printing technology for ultra fine pitch flip

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